原文来自清华大学电子工程系：
https://mp.weixin.qq.com/s/TwxLg2Ter2AjHkT7mag-vQ
Due to its inherent advantages of high speed, wide bandwidth, and parallel propagation, light is well suited to address the computational power challenges posed by the massive linear calculations in artificial intelligence. However, existing optical linear computing architectures often rely on complex beam interactions to perform vector multiply-accumulate operations, and also depend on a large number of DACs (digital-to-analog converters) for electro-optic modulation. Consequently, it is difficult to simultaneously achieve both dimension scalability and arbitrary programmability – two essential requirements for a general-purpose computing chip. Such architectures are therefore typically used as application-specific chips for particular tasks to minimize the need for programming the optical computing units.
Recently, the research group of Xue Feng and Yongzhuo Li from Professor Yidong Huang’s team at the Department of Electronic Engineering, Tsinghua University, has made progress in general-purpose linear optical computing. They proposed a computing architecture named the “Photonic Abacus”. This architecture uses independent “light source-detector pairs” as its basic computational units, called “photonic abacus beads”. Multiply-accumulate operations are performed by encoding the data to be computed onto the light source and the detector, respectively. Moreover, a novel spatiotemporal coding quantization scheme is adopted for hybrid analog-digital computing. The data to be computed are encoded through the on/off states of the “photonic abacus beads” in both time and space, eliminating the need for DACs for digital-to-analog conversion. This method is quite similar to the operation of a traditional Chinese abacus. Therefore, the “Photonic Abacus” architecture perfectly solves the two aforementioned problems of linear optical computing. By copying, reconfiguring, and encoding the “photonic abacus beads”, the Photonic Abacus can achieve arbitrary dimension expansion while maintaining reconfigurability and programmability, and it largely avoids the latency, power consumption, and area overhead caused by DACs in conventional electro-optic modulation. The Photonic Abacus architecture marks an important step for optical computing moving from application-specific chips toward general-purpose chips.
Experimentally, the research team constructed a 64-dimensional Photonic Abacus using a 64-channel VCSEL chip and a molybdenum telluride (MoTe₂) 2D material detector chip. In randomly generated vector inner-product tests, the system achieved a computational fidelity exceeding 98%. Furthermore, using this Photonic Abacus, the team reached 88% classification accuracy on the MNIST handwritten digit recognition task and successfully solved a 1024-dimensional randomly generated Ising problem – the highest dimension reported to date for an optically simulated annealing Ising machine.
On January 1, 2026, the related research results were published online in the journal Light: Science & Applications under the title “SUANPAN: scalable photonic linear vector machine”.
Ziyue Yang and Chen Li, PhD students of the Class of 2022 in the Department of Electronic Engineering, Tsinghua University, are co-first authors of the paper. Associate Professor Xue Feng, Associate Researcher Yongzhuo Li, and Prof. Yidong Huang are the corresponding authors. Collaborating institutions include Peking University, Shenzhen Berxel Photonics Co., Ltd, and Shenzhen Technology University. The research was supported by the National Key Research and Development Program of China and the National Natural Science Foundation of China.
Photonic Abacus computing architecture
Photonic Abacus performing multiple computing tasks
Paper information:
Paper link: https://www.nature.com/articles/s41377-025-02059-7
